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74F524 8-Bit Registered Comparator
April 1988 Revised August 1999
74F524 8-Bit Registered Comparator
General Description
The 74F524 is an 8-bit bidirectional register with parallel input and output plus serial input and output progressing from LSB to MSB. All data inputs, serial and parallel, are loaded by the rising edge of the input clock. The device functions are controlled by two control lines (S0, S1) to execute shift, load, hold and read out. An 8-bit comparator examines the data stored in the registers and on the data bus. Three true-HIGH, open-collector outputs representing "register equal to bus", "register greater than bus" and "register less than bus" are provided. These outputs can be disabled to the OFF state by the use of Status Enable (SE). A mode control has also been provided to allow twos complement as well as magnitude compare. Linking inputs are provided for expansion to longer words.
Features
s 8-Bit bidirectional register with bus-oriented input-output s Independent serial input-output to register s Register bus comparator with "equal to", "greater than" and "less than" outputs s Cascadable in groups of eight bits s Open-collector expansion comparator outputs for AND-wired
s Twos complement or magnitude compare
Ordering Code:
Order Number 74F524SC 74F524PC Package Number M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
(c) 1999 Fairchild Semiconductor Corporation
DS009546
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74F524
Unit Loading/Fan Out
U.L. Pin Names S0 , S1 C/SI CP SE M I/O0-I/O7 Description HIGH/LOW Mode Select Inputs Status Priority or Serial Data Input Clock Pulse Input (Active Rising Edge) Status Enable Input (Active LOW) Compare Mode Select Input Parallel Data Inputs or 3-STATE Parallel Data Outputs C/SO LT EQ GT
Note 1: OC = Open Collector
Input IIH/IIL Output IOH/IOL 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 20 A/-0.6 mA 70 A/-0.65 mA -3 mA/24 mA (20 mA) -1 mA/20 mA (Note 1) /20 mA (Note 1) /20 mA (Note 1) /20 mA
1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 1.0/1.0 3.5/1.083 150/40 (33.3) 50/33.3 OC (Note 1) /33.3 OC(Note 1) /33.3 OC(Note 1) /33.3
Status Priority or Serial Data Output Register Less Than Bus Output Register Equal Bus Output Register Greater Than Bus Output
Number Representation Select Table
M L H Magnitude Compare Twos Complement Compare Operation
Select Truth Table
S0 L L S1 L H Operation Hold--Retains Data in Shift Register Read--Read Contents in Register onto Data Bus, Data Remains in Register Unaffected by Clock H H L H Shift--Allows Serial Shifting on Next Rising Clock Edge Load--Load Data on Bus into Register
Status Truth Table
(Hold Mode) Inputs SE H L X H H H L C/SI H L L L H H H Data Comparison X OA-OH > I/O0-I/O7 OA-OH = I/O0-I/O7 OA-OH < I/O0-I/O7 OA-OH > I/O0-I/O7 OA-OH = I/O0-I/O7 OA-OH < I/O0-I/O7 EQ H L H L L H L Outputs GT H H H H H L L LT H H H H L L H C/SO 1 L L L L H L
1 = HIGH if data are equal, otherwise LOW H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial
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74F524
Functional Description
The 74F524 contains eight D-type flip-flops connected as a shift register with provision for either parallel or serial loading. Parallel data may be read from or loaded into the registers via the data bus I/O0-I/O7. Serial data is entered from the C/SI input and may be shifted into the register and out through the C/SO output. Both parallel and serial data entry occur on the rising edge of the input clock (CP). The operation of the shift register is controlled by two signals S0 and S1 according to the Select Truth Table. The 3-STATE parallel output buffers are enabled only in the Read mode. One port of an 8-bit comparator is attached to the data bus while the other port is tied to the outputs of the internal register. Three active-OFF, open-collector outputs indicate whether the contents held in the shift register are "greater than", (GT), "less than" (LT), or "equal to" (EQ) the data on the input bus. A HIGH signal on the Status Enable (SE) input disables these outputs to the OFF state. A mode control input (M) allows selection between a straightforward magnitude compare or a comparison between twos complement numbers. For "greater than" or "less than" detection, the C/SI input must be held HIGH, as indicated in the Status Truth Table. The internal logic is arranged such that a LOW signal on the C/SI input disables the "greater than" and "less than" outputs. The C/SO output will be forced HIGH if the "equal to" status condition exists, otherwise C/SO will be held LOW. These facilities enable the 74F524 to be cascaded for word length greater than eight bits. Word length expansion (in groups of eight bits) can be achieved by connecting the C/SO output of the more significant byte to the C/SI input of the next less significant byte and also to its own SE input (see Figure 1). The C/SI input of the most significant device is held HIGH while the SE input of the least significant device is held LOW. The corresponding status outputs are AND-wired together. In the case of twos complement number compare, only the Mode input to the most significant device should be HIGH. The Mode inputs to all other cascaded devices are held LOW. Suppose that an inequality condition is detected in the most significant device. Assuming that the byte stored in the register is greater than the byte on the data bus, the EQ and LT outputs will be pulled LOW and the GT output will float HIGH. Also the C/SO output of the most significant device will be forced LOW, disabling the subsequent devices but enabling its own status outputs. The correct status condition is thus indicated. The same applies if the registered byte is less than the data byte, only in this case the EQ and GT outputs go LOW and LT output floats HIGH. If an equality condition is detected in the most significant device, its C/SO output is forced HIGH. This enables the next less significant device and also disables its own status outputs. In this way, the status output priority is handed down to the next less significant device which now effectively becomes the most significant byte. The worst case propagation delay for a compare operation involving "n" cascaded 74F524s will be when an equality condition is detected in all but the least significant byte. In this case, the status priority has to ripple all the way down the chain before the correct status output is established. Typically, this will take 35 + 6(n-2) ns.
Function Diagram
FIGURE 1. Cascading 74F524s for Comparing Longer Words
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74F524
Block Diagram
Notes: 1. 3-STATE Output 2. Open-Collector Output
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74F524
Absolute Maximum Ratings(Note 2)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 3) Input Current (Note 3) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to VCC -0.5V to +5.5V -65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C +4.5V to +5.5V
Note 2: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 3: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 10% VCC 10% VCC 5% VCC 5% VCC VOL IIH IBVI ICEX VID IOD IIL IIH + IOZH IIL + IOZL IOS IOHC ICCH ICCL ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Current Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Open Collector, Output OFF Leakage Test Power Supply Current Power Supply Current Power Supply Current 128 128 128 -60 4.75 3.75 -0.6 70 -650 -150 250 180 180 180 10% VCC 10% VCC 2.5 2.4 2.7 2.7 0.5 0.5 5.0 7.0 50 V A A A V A mA A A mA A mA mA mA Min Max Max Max 0.0 0.0 Max Max Max Max Min Max Max Max V Min Min 2.0 0.8 -1.2 Typ Max Units V V V Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -1 mA IOH = -3 mA IOH = -1 mA IOH = -3 mA IOL = 20 mA (I/On) IOL = 24 mA (LT, GT, EQ, C/SO) VIN = 2.7V VIN = 7.0V VOUT = VCC (I/On, C/SO) IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V VI/O = 2.7V VI/O = 0.5V VOUT = 0V VOUT = VCC VO = HIGH VO = LOW VO = HIGH Z
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74F524
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Shift Frequency Propagation Delay I/On to EQ Propagation Delay I/On to GT Propagation Delay I/On to LT Propagation Delay I/On to C/SO Propagation Delay CP to EQ Propagation Delay CP to GT Propagation Delay CP to LT Propagation Delay CP to C/SO (Load) Propagation Delay CP to C/SO (Serial Shift) Propagation Delay C/SI to GT Propagation Delay C/SI to LT Propagation Delay S0, S1 to C/SO Propagation Delay SE to EQ Propagation Delay SE to GT Propagation Delay SE to LT Propagation Delay C/SI to C/SO Propagation Delay M to GT Propagation Delay M to LT Propagation Delay S0, S1 to EQ Propagation Delay S0, S1 to GT Propagation Delay S0, S1 to LT Output Enable Time S0, S1 to I/On Output Disable Time S0, S1 to I/On 50 9.0 5.0 8.5 6.5 7.0 4.5 8.0 6.0 10.0 4.0 10.0 8.5 9.0 5.5 8.5 5.0 4.5 9.0 3.0 8.0 3.5 6.5 5.5 3.5 2.5 6.5 3.5 5.0 3.5 4.0 4.0 8.0 6.0 8.0 4.5 15.0 9.0 10.5 10.5 13.0 12.0 4.5 5.5 3.5 4.5 VCC = +5.0V CL = 50 pF Typ 75 16.5 9.5 14.1 13.0 15.5 10.0 15.2 12.5 20.0 8.5 16.5 17.0 20.0 13.5 16.5 10.0 9.0 15.0 6.5 15.5 6.5 11.5 14.0 8.0 6.0 12.5 6.0 10.5 6.0 8.5 8.5 15.0 12.0 17.0 9.5 25.0 15.0 18.0 18.0 22.0 19.0 10.0 11.0 8.0 9.6 20.0 12.0 19.0 16.5 20.0 14.0 19.5 16.0 25.0 16.5 21.0 22.0 25.0 17.0 21.0 13.0 11.5 19.0 8.5 20.0 8.5 14.5 18.0 10.5 8.0 16.0 8.0 13.5 8.0 11.0 11.0 19.5 17.5 22.0 12.0 33.0 19.0 23.0 23.0 28.0 24.0 13.0 15.0 12.0 12.5 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 50 9.0 5.0 8.5 6.5 7.0 4.5 8.0 6.0 10.0 4.0 10.0 8.5 9.0 5.5 8.5 5.0 4.5 9.0 3.0 8.0 3.5 6.5 5.5 3.5 2.5 6.5 3.5 5.0 3.5 4.0 4.0 8.0 6.0 8.0 4.5 15.0 9.0 10.5 10.5 13.0 12.0 4.5 5.5 3.5 4.5 21.0 13.0 20.0 17.5 21.0 15.0 20.5 17.0 26.0 17.5 22.0 23.0 26.0 18.0 22.0 14.0 12.5 20.0 9.5 21.0 9.5 15.5 19.0 11.5 9.0 17.0 9.0 14.5 9.0 12.0 12.0 20.5 18.5 23.0 13.0 35.0 20.0 24.0 24.0 30.0 25.0 14.0 16.0 13.0 13.5 ns ns ns ns ns ns ns ns ns ns ns Max MHz Units
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74F524
AC Operating Requirements
TA = +25C Symbol Parameter VCC = +5.0V Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) Setup Time, HIGH or LOW I/On to CP Hold Time, HIGH or LOW I/On to CP Setup Time, HIGH or LOW S0 or S1 to CP Hold Time, HIGH or LOW S0 or S1 to CP Setup Time, HIGH or LOW C/SI to CP Hold Time, HIGH or LOW C/SI to CP Clock Pulse Width, HIGH 6.0 6.0 0 0 10.0 10.0 0 0 7.0 7.0 0 0 5.0 Max TA = 0C to +70C VCC = +5.0V Min 6.0 6.0 0 0 10.0 10.0 0 0 7.0 7.0 0 0 5.0 ns ns ns ns Max Units
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74F524
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B
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74F524 8-Bit Registered Comparator
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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